Why CMOS (complementary metal-oxide semiconductor) uses matched pairs of P-channel and N-channel MOSFETs so that in either stable logic state one transistor of the pair is off, leaving essentially no DC path from supply to ground. Current is drawn mainly during switching transitions, to charge and discharge capacitance, so static power consumption is extremely low. That is why CMOS dominates battery-powered and large-scale digital designs.
Watch out ECL is the opposite extreme: its transistors are kept in the active region and never saturate, which makes it the fastest but the most power-hungry family. TTL variants, including Schottky, draw steady bias current through their input and output stages, and NMOS logic conducts through a pull-up load whenever the output is low.
CMOS = Complementary pairs, so one is always off: near-zero idle current. ECL is fastest but thirstiest.