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E6C04

CIRCUIT COMPONENTS · Digital ICs: families of digital ICs; gates; programmable logic devices

E6C04E6C →

Which of the following is an advantage of BiCMOS logic?

  1. AIts simplicity results in much less expensive devices than standard CMOS
  2. BIt is immune to electrostatic damage
  3. CIt has the high input impedance of CMOS and the low output impedance of bipolar transistors
  4. DAll these choices are correct
Why BiCMOS puts CMOS and bipolar transistors on the same die so each does what it does best. The CMOS input stage gives very high input impedance, so it barely loads the driving circuit, while bipolar output transistors provide low output impedance and high current drive for fast switching of capacitive loads. You get CMOS's low static power at the input together with bipolar's drive strength at the output.
Watch out The cost claim is backwards: fabricating both device types on one chip takes extra mask steps, so BiCMOS is more complex and more expensive than plain CMOS. And the CMOS gate inputs still have thin oxide, so BiCMOS is just as vulnerable to static discharge.
BiCMOS = best of Bi and CMOS: CMOS in (high Z), bipolar out (low Z, big drive).
HamSandwich explanation, first draft. The question and answers are the NCVEC text.
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The rest of E6C

  1. E6C01 What is the function of hysteresis in a comparator?
  2. E6C02 What happens when the level of a comparator's input signal crosses the threshold voltage?
  3. E6C03 What is tri-state logic?
  4. E6C04 Which of the following is an advantage of BiCMOS logic?
  5. E6C05 Which of the following digital logic families has the lowest power consumption?
  6. E6C06 Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?
  7. E6C07 What best describes a pull-up or pull-down resistor?
  8. E6C08 In Figure E6-3, which is the schematic symbol for a NAND gate?
  9. E6C09 What is used to design the configuration of a field-programmable gate array (FPGA)?
  10. E6C10 In Figure E6-3, which is the schematic symbol for a NOR gate?
  11. E6C11 In Figure E6-3, which is the schematic symbol for the NOT operation (inversion)?
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